1. Field of the Invention
The present invention relates to an analog-to-digital conversion apparatus and a method of analog-to-digital conversion
2. Description of the Related Art
There is a case that a plurality of analog signals needs to be converted into digital signals. In such a case, it is not economically efficient to provide an analog-to-digital (A/D) conversion apparatus for each analog signal. Therefore, an A/D converter has been proposed, in which an A/D converter is provided for a plurality of analog signals and the A/D conversion can be carried out while switching the analog signals.
A conventional A/D conversion apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-88723). FIG. 1 shows a configuration of the conventional A/D conversion apparatus. Referring to FIG. 1, the conventional A/D conversion apparatus includes a channel register 52, a multiplexer 54, an A/D converter 56, a result storage buffer 58, a CPU 60, a bus 62, and a control unit 70. The multiplexer 54 selects one of a plurality of analog input terminals in response to an input terminal specification signal from the channel register 52. The A/D converter 56 converts an analog signal on the analog input terminal selected by the multiplexer 54, into a digital signal. The conversion result is stored in the result storage buffer 58. The control unit 60 outputs the input terminal specification signal to the multiplexer 54 based on an optionally specified order of the A/D conversion.
This conventional A/D conversion apparatus has a select mode and a scan mode. For instance, as shown in FIG. 2, when a channel specification data is stored in the channel register 52 to specify a channel “3”, only the analog signal on the input channel “CH3” is converted into a digital signal in the select mode. On the other hand, in the scan mode, all the input terminals are sequentially selected based on the channel specification data stored in the register 52, and the analog signal on the selected input terminal is converted into the digital signal. Therefore, in the above-mentioned conventional A/D conversion apparatus, a conversion cycle of each analog signal cannot be changed even if the conversion cycle of the A/D conversion is different in each analog signal. When the conversion cycle should be optionally changed, it is necessary to set the channel specification data in the above-mentioned register 52 again after the CPU accepts an interrupt. However, in this case, the A/D conversion is not carried out until new channel specification data is set. Considering a period to accept the interrupt and occupation of a bus by a DMA unit, an idling period of the A/D converter becomes irregular. Therefore, time scheduling is never achieved without using a circuit that operates constantly such as a timer. In addition, a limitation of allocation of channels and a load of software processing by the CPU are caused.
For this reason, a channel specification data shown in FIG. 3 has been used to set the input terminal of analog signal flexibly. Referring to FIG. 3, in the channel specification data, a start channel of the A/D conversion (input terminal) is specified with four lower bits. An end channel of the A/D conversion is specified with the four upper bits. The analog signals of the channels within the specified range can be converted into the digital signals by using such channel specification data depending on the conversion cycle.
However, even in the A/D conversion apparatus using such channel specification data, the next channel specification data cannot be set during the A/D conversion. Therefore, an A/D converter stops intermittently and it is not efficient as well as the conventional A/D conversion apparatus shown in FIG. 1. Also, it is impossible to select only a necessary channel because channels in a range are specified.